pcb design

Chips with an IC pin center distance of less than 0.65mm on FS Technology’s circuit boards should have a Mark point corresponding to the chip positioning on the diagonal of the long side of the IC; when there are patches on both sides of the pcb, both sides of the pcb should be Add Mark points based on this article.

2. The edge of the PCB should retain the 5mm process edge (the minimum spacing requirement for the machine to clamp the PCB).

Chips whose center-to-center distance between IC pins is less than 0.65mm should be greater than 13mm from the edge of the board (including the edge of the process); the four corners of the board should be chamfered with a φ5 arc. Judging from the current bending degree of PCB wings, the optimal splicing length is about 200mm (equipment processing size: maximum length is 330mm; maximum width is 250mm), try not to spell in the width direction to prevent bending during production.

3. MARK point functions and categories.

Mark points, also known as fiducials, provide a common measurable point for all steps in the assembly process to ensure that each assembly device can accurately locate the circuit pattern. Therefore, FS Technology believes that the Mark point is crucial for SMT production.

4. MARK point design specification recommended by our department.

1) Shape: It is recommended to mark the Mark point as a diameter: R=1.0mm solid circle;
2) Form a complete MARK point, including marked points (or feature points) and open areas.
3) Position: The Mark point is located at the relative position of the diagonal on the veneer or puzzle, and is separated as much as possible; it is best to distribute it at the longest diagonal position (such as the MARK point position diagram).
4) In order to ensure the installation accuracy requirements of FS Technology, SMT requirements: each PCB must have at least one pair of MARK points for the SMT machine to identify, and there must be a single-board MARK (when assembling).
Panel MARK or combined MARK only play a role of auxiliary positioning.
5) When assembling, the relative positions of the MARK points of each single board must be the same.
The position of the MARK point cannot be moved for any reason, resulting in asymmetrical position of the MARK point of each board;
6) All MARK points on the PCB are only valid: two MARKs appearing in pairs on the same diagonal are valid.
So MARK points must appear in pairs to be used (MARK point location map).

7) The distance between the MARK point (edge ​​of the open area) and the edge of the PCB must be ≥5.0mm (minimum spacing requirements for the machine to clamp the PCB)

8) Requirements for open areas.

Around the mark point marking, there must be an open area with no other circuit features or markings.
The radius of the circle in the open area is R≥2R, where R is the radius of the MARK point.
When R reaches 3R, the machine recognition effect is better.

9) PBC Materials

Mark point markings can be bare copper, which is protected by a transparent anti-oxidant coating. If solder mask (solder mask) is used, the mark point or its open area should not be covered.

10) PBC Contrast.

A. The best identification performance is achieved when there is a high contrast between the mark point markings and the matrix material of the printed board.
B. The internal background must be the same for all mark points.
MARK classification:
1) Mark points are used for solder paste printing and component placement optical positioning.
According to the function of Mark points on the PCB, it can be divided into panel Mark points, single-board Mark points, local Mark points (also known as device-level Mark points),
2) There should be at least three Mark points on the edge of the FS technology paneling process and the veneer that does not need paneling, distributed in an L shape, and the diagonal Mark points are asymmetrical about the center.
3) If there are mounted components on both sides, then there must be mark points on each side.
4) There should be mark points on the board that needs to be assembled as much as possible. If there is no place to place the mark point, the mark point cannot be placed on the board.
5) For QFP with lead center distance ≤ 0.5mm and BGA equipment with center distance ≤ 0.8mm, the local Mark point should be set near the diagonal of the component center point for accurate positioning.
6) If several SOP devices are relatively close (≤100 mm) to form an array, they can be regarded as a whole, and two local Mark points are designed at their diagonal positions.

Optical Fiducial PCB Design-FS Technology

On a PCB with a patch, in order to locate the entire PCB, it is usually necessary to place the optical positioning points on the four corners of the PCB, generally three.
Common reference points mainly include three types of board reference points, unit reference points and local reference points.

1. Reference point structure

(1) Panel datum point and unit datum point.

Shape/Size: 40mil diameter solid circle.
FS Technology Solder Mask Window: A circle concentric with the reference point, the size is twice the diameter of the reference point.
A 2mm diameter edge requires a round or octagonal copper wire as a guard ring.
The internal background of the optical positioning reference symbols on the same board should be the same, that is, whether there is copper foil under the three reference symbols should be consistent.

(2) Local datum point.

Parts such as QFP and pitch ≤0.4mm BGA, CSP, FC need to place local fiducials.
Size/Shape: Solid circle, 40mil diameter.
Solder mask opening: The size is processed according to the ordinary pad, and the outer ring copper ring cannot.

2. Place the datum point:

General principles:

The veneer for processing SMT equipment must be placed with fiducial points.
The number of single-sided reference points is greater than or equal to 3.
For single-sided layout, simply place the datum point on the component face.
..When A5I5^0L-z1m+PPCB is double-sided layout, the fiducials are placed on both sides.
For the datum points placed on both sides, except for mirror splicing, the positions of the datum points on both sides are basically the same.

(1) The reference point for FS Technology to place the puzzle.

Panel datum points and cell datum points need to be placed.
There are three panel fiducials and unit fiducials.
The edges of the board are distributed in an L shape, and keep them as far away as possible.
Figure A below shows the location requirements for the panel datum points.
When using a mirror-symmetrical panel, the reference point on the auxiliary side must meet the requirements of overlapping after flipping, as shown in Figure B below.

(2) The datum point for placing the cell board.

The number of reference points is three, distributed in an L shape on the edge of the board, and the distance between each reference point should be as far as possible.
The edge of the reference point must be greater than 5mm.
If all four edges are not guaranteed to be satisfied, the transmission edge should at least satisfy the requirements.
 

ESD Suppression Stop PCB Design-FS Technology

PCB wiring is a key factor in ESD protection, FS Technology believes that a reasonable PCB design can reduce unnecessary costs caused by fault inspection and rework. In PCB design, it is more important to overcome the electromagnetic interference (EMI) electromagnetic field effect generated by the discharge current, because the transient voltage suppression stopper (TVS) diode is used to suppress the direct charge injection caused by the ESD discharge.

This article will provide optimized ESD protection for PCB design criteria.

1. Circuit loop.

When current enters circuit loops by induction, these loops are closed and have variable magnetic flux. The current range is proportional to the area of ​​the ring. Larger loops contain more magnetic flux and therefore have stronger current induction in the circuit. Therefore, the loop area must be reduced. The most common loop consists of power and ground wires.

Multilayer PCB designs employ power and ground planes, where possible. Multilayer circuit boards not only minimize the circuit area between power and ground, but also reduce the high-frequency EMI electromagnetic fields generated by ESD pulses. If multilayer boards were not possible, FS Technology would have to connect the circuits for the power and ground lines into a grid. The grid connection can play the role of power and ground, and the printed lines of each layer should pass through holes and the connection interval in each direction should be within 6 cm. In addition, when wiring, the power and ground printed lines produced by FS Technology are as close as possible, which can also reduce the loop area.

Another way to reduce loop area and induced current is to reduce parallel paths between interconnects. When a signal cable longer than 30 cm must be used, a protective wire can be used. A better approach is to place the ground near the signal lines. The signal line should be within 13mm of the protection line or grounding line. Arrange long signal wires (>30cm) or power wires and their ground wires of each sensitive element in a crossover. Crossovers must be separated from top to bottom or left to right.

2. The length of the circuit connection.

Long signal lines can also be used as antennas for receiving ESD pulse energy. Trying to use short signal lines can reduce the efficiency of antennas receiving ESD electromagnetic fields. In order to reduce the printed line length of the interconnection, FS Technology will try to place the interconnection equipment in the adjacent position.

3. Inject the ground charge.

Direct discharge of ESD to the ground plane can damage sensitive circuits. Use one or more high frequency bypass capacitors between the power and ground of the consumables. Bypass capacitors reduce charge injection and maintain the voltage difference between the power and ground ports. The TVS shunts the induced current, maintaining the potential difference of the TVS clamping voltage. To reduce parasitic inductive effects, TVS and capacitors should be placed as close as possible to the protected IC.